1. Field of the Invention
The present invention relates to the field of semiconductor fabrication; more specifically, it relates a method of fabricating doped polysilicon lines and complementary metal-oxide-silicon (CMOS) doped polysilicon gates.
2. Background of the Invention
Advanced CMOS devices utilize doped polysilicon lines and gates with metal silicide layers as a method of improving and matching the performance of N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs). However, controlling the width and sheet resistance of oppositely doped polysilicon lines and gates has become more important and difficult as the widths of polysilicon lines and gates have decreased. Therefore, there is a need for a method of fabricating doped polysilicon lines and gates with improved linewidth control.